1. Field of the Invention
The present invention relates to a controller for power transducers such as UPS's (uniterruptable power source units) and SIV's which comprise DC/AC power transducer circuits (hereinafter referred to as inverters).
2. Description of Related Art
FIG. 8 is a block diagram illustrating a configuration of a control circuit for instantaneous control inverters which is described in "Composing Method for Moninteracting Control System for PWK Inverters by Matrix Technique" published as a collection of lecture monographs at 77th to 81st Power Electronics Research Meetings, Vol 14 (1988) p128-137. In this control circuit, a three-phase inverter output current supplied from an inverter 1 used as a power transducer is provided through current sensors 4, 5, and 6 to a filter 2 of inductors and capacitors. The inverter output passes through the filter 2 and is supplied to a load circuit 3.
Since three-phase inverter output current is detected as DC components by the current sensors 4, 5 and 6, this current is converted by a three-phase/dq axis converter circuit 105 into a d-axis current and a q-axis current which have a reference frequency and a normal phase.
Three-phase output voltages VLu, VLV and VLw supplied from the inverter 1 to the load circuit 3 are detected by a voltage sensor 7. The detected three-phase output voltages VLu, VLv and VLw are converted by a three-phase/dq axis converter circuit 114 into a d axis voltage VLd and a q axis voltage VLq having the reference frequency and the normal phase and input into a subtracter 116.
The subtracter 116 calculates deviations by subtracting a VLd command and a VLg command which are provided from a voltage command circuit 115 from the d axis voltage VLd and the q axis voltage VLq respectively having the reference frequency and the normal phase which are output from the three-phase/dq axis converter circuit 114.
On the basis of the deviations calculated by the subtracter 116, a voltage control circuit 100 outputs a current d command and a current q command so that VLu, VLv and VLw which are the output voltages of the inverter 1 are in accordance with a VLd command and a VLq command which are voltage commands. The current d command and current q command are restricted by a limiter 101 so as not to exceed a maximum passage current and output to a current control circuit 102. On the basis of the current d command and current q command as well as the d axis current and the q axis current having the reference frequency and normal phase, a current control circuit 102 outputs a current command for the inverter 1 to a dq axis/three phase converter circuit 103.
On the basis of the current command for the inverter 1, the dq axis/three-phase phase converter circuit 103 converts the d axis current and q axis current into a three-phase inverter output current command. In accordance with the three-phase inverter output current command, a gate signal generator circuit 104 generates a gate signal in a power semiconductor switching element of the inverter 1.
As clear from the configuration described above, the conventional control circuit for the instantaneous control inverters is configured to allow the voltage control circuit 100 to receive as inputs the deviations between the voltage commands and detected voltage values from the subtracter circuit 116, and output the current commands so that the output voltages are in accordance with the voltage commands. The current commands are restricted by the limiter 101 so as not to exceed the maximum passage voltage. The current control circuit 102 performs current control operations so that currents are supplied in accordance with the restricted current d command and current q command. As a result, the control circuit prevents a current supplied through the power semiconductor of the inverter 1 from exceeding the maximum passage current, thereby protecting the power semiconductor from damage.
When a single phase load is connected to the inverter control circuit which has the configuration described above, the voltage control circuit operates so as to cancel the three-phase unbalanced voltages. However, a steady-state deviation is produced due to a control response. In other words, an inverter of this kind has switching frequencies of 5 to 15 kHz and can respond only at 5000 to 15000 rad/sec. When a fundamental frequency is set at 60 Hz, for example, a harmonic of the eleventh order is at 660 Hz and approximately 4150 rad/sec, and response speed about five times as high, or at least 20750 rad/sec is necessary for control while following this harmonic. The conventional inverter control circuit has a Control response too slow for the harmonic and allows the steady-state deviation to be produced.
A conventional control circuit which corrects the three-phase unbalanced voltages, i.e. an inverter control circuit applied to a three-phase output voltage enhancing system of an uninterruptable power source unit, is disclosed by Japanese Patent Laid-Open Ko. 6-38538. This inverter control circuit is configured to detect three-phase voltages independently and control an inverter on the basis of a deviation between a mean value of the single-phase voltages subjected to full-wave rectification and a mean value (Vset) of the three-phase voltages subjected to full-wave rectification. However, this inverter control circuit is configured for voltage control only and cannot adopt the current control circuit 102 used in the conventional example shown in FIG. 8, thereby being incapable of protecting a switching element composing an inverter 1 from an overcurrent.
The conventional inverter control circuit which is configured as described above operates to cancel the three-phase unbalanced voltages when a load is connected thereto but allows a steady-state deviation to be produced due to the control response. Further, when the control circuit is to be operated by software processing and a micro computer which has a slow processing speed is adopted for implementing the control circuit at a low cost, the control response is further slowed down and the steady-state deviation is enlarged.